1. Field of the Invention
The invention relates in general to a memory access method and device, and more particularly to an over-driven access method and device for ferroelectric memory.
2. Description of the Related Art
Ferroelectric memory uses ferroelectric capacitor as the storage medium. Ferroelectric capacitor can be polarized to different polarized states, and thus can represent the stored data by means of polarized states. Please refer to FIG. 1, a transitional diagram illustrating the transition of the polarized state of ferroelectric capacitor. The transition of the polarized state of ferroelectric capacitor is hysteresis which means that a greater-than-zero voltage must be applied in order to convert the polarization of a ferroelectric capacitor from a negative state into a positive state and that a smaller-than-zero voltage must be applied in order to convert the polarization of a ferroelectric capacitor from a positive state into a negative state. Seeing that the polarized state of ferroelectric capacitor still can be sustained even in the absence of power supply, the ferroelectric capacitor does have the potential to replace the flash memory which is in current use now. Moreover, the polarized state of ferroelectric capacitor can be changed when the voltage applied onto the ferroelectric capacitor changes, thus has the potential to replace the dynamic random access memory (DRAM) as well.
Apart from having the characteristic of hysteresis, the ferroelectric capacitor has another characteristic, i.e., its capacitance is changeable. The formula for capacitance C is: C=ΔQ/ΔV, wherein Q is the quantity of electric charges; Q is the voltage drop of capacitor. The polarization of ferroelectric capacitor P is proportional to the quantity of electric charges Q, therefore capacitance C is proportional to the slope of the transition curve for polarization in FIG. 1. The larger the slope is, the greater the capacitance will be. It can be inferred from FIG. 1 that the capacitance during polarity transition is larger than that in a stabilized state.
Please refer to FIG. 2A, a schematic diagram illustrating a memory unit of a ferroelectric memory. This memory unit which is in the form of 1T1C consists of one transistor, T, and one ferroelectric capacitor, Cf, with one end of ferroelectric capacitor Cf being coupled to plate line PL. When word line WL is enabled, the voltage drop in ferroelectric capacitor Cf is exactly the voltage difference between plate line PL and bit line BL. Please refer to FIG. 2B, a schematic diagram illustrating another memory unit of a ferroelectric memory. This memory unit which is in the form of 2T2C consists of two transistor, T and T′, and two ferroelectric capacitors, Cf and Cf′. Every memory unit further comprises a sense amplifier SA which is used to amplify the voltage difference between bit line BL and bit line BL′ to facilitate the access to the data stored at the ferroelectric memory. Sense amplifier SA as illustrated in FIG. 2B is a latch sense amplifier further comprising two phase inverters which raises the voltage in the high-voltage bit line to be even higher and reduces the voltage in the low-voltage bit line to be even lower. Sense amplifier SA is initiated when sense amplifier enabling signal SAE is received.
General speaking, there are two methods for the access of ferroelectric memory: the plate-line driven method and the bit-line driven method. Please refer to FIG. 3, a timing chart when plate-line driven method is used to access the ferroelectric memory using the ferroelectric memory in FIG. 2 as an example. At the initial stage, P and P′, the polarized state of ferroelectric capacitor Cf and that of ferroelectric capacitor Cf′, are of positive polarity and negative polarity respectively. Firstly, enable word line WL during period T1 such that transistors T and T′ can be conducted. Next, enable plate line PL during period T2 and raise the voltage in plate line PL to high level. Since the voltage drop of ferroelectric capacitors Cf and Cf′ has changed to be positive, their polarized states P and P′ as shown in the diagram become positive as well. With the change in polarity from negative to positive, the capacitance of ferroelectric capacitor Cf′ becomes larger and stores more electric charges causing bit line BL′ to have a higher voltage accordingly. Following that, enable sensing g amplifier SA to enlarge the voltage difference between bit line BL and bit line BL′ to facilitate the identification of the data stored at the memory unit. Meanwhile, the voltage in bit line BL′ whose voltage is higher will be raised to high level; the voltage in bit line BL whose voltage is lower will be reduced to low level. The voltages in bit line BL′ and the voltage in plate line PL are both at high levels, so the voltage drop in ferroelectric capacitor Cf′ nears zero. The transition for the polarized state P which still remains positive is shown in the diagram. The abovementioned period T1 and T2 are driving stage during which time bit line voltages are differentiated; period T3 is sensing stage.
During period T3, P′, the polarity of ferroelectric capacitor Cf′ which was originally negative prior to accessing stage, becomes positive. In order to restore the original polarized state for ferroelectric capacitor Cf′, some recovery procedures need to be taken. First, disable plate line PL during period T4, so that P′, the polarized state of ferroelectric capacitor Cf′, will become negative for the voltage drop in ferroelectric capacitor Cf′ has already turned negative. Next, disable sense amplifier SA during period T5 such that the voltage in bit line BL will drop immediately causing the voltage drop in ferroelectric Cf′ to be reduced to zero. The original polarized state will thus be restored.
The plate-line driven method enables plate line PL and word line WL first causing bit lines BL and BL′ to generate different voltages according to the polarized states of ferroelectric capacitors Cf and Cf′. The bit-line driven method enables bit lines BL and BL′ before enabling word line WL, so that bit lines BL and BL′ can generate different voltages according to the polarized states of ferroelectric capacitors Cf and Cf′. This has been understood by those who are conventional with this technology and will not be repeated here.
In order to further improve access quality, an over-driven access method is proposed in “A 76 mm2 8 Mb Chain Ferroelectric Memory” (ISSCC, 2001). Please refer to FIG. 4, a schematic diagram for ferroelectric memory 400 according to a conventional over-driven access method. Ferroelectric memory 400 differs from the abovementioned ferroelectric memories in that bit lines BL and BL′ are respectively connected to transistors Q and Q′ and to capacitors Cov and Cov′. Please refer to FIG. 5, a timing chart according to a conventional over-driven method. Suppose the polarized states of cells CL and CL′ are negative and positive respectively at the initial stage. The over-driven access method is used to assist the abovementioned plate-line driven method or bit-line driven method. In the present example, over-driven access method is used to assist plate-line driven method. First, raise the voltage in plate line PL at time t1. Since the polarity of cell CL has already changed from negative to positive, cell CL will have a larger capacitance and have more electric charges to be coupled to bit line BL. Consequently, the voltage in bit line BL will be higher than that in BL′ with a voltage difference of Δv1. Next, reduce over-driven voltage ODV at time t3, so that the voltages in bit lines BL and BL′ will drop accordingly. Owing to a larger capacitance in cell CL, the voltage in bit line BL will drop slower than that in bit line BL′. Due to the introduction of over-driven voltage OVD, Δv2, the voltage difference between bit line BL and bit line BL′, is enlarged and is greater than Δv1. Last, initiate sense amplifier SA at time t5 to raise the voltage in bit line BL to high level and reduce the voltage in bit line BL′ to low level. The contents stored at the present memory unit will be able to be accessed. However, more capacitors and transistors are required in this method resulting in an increase in chip size and manufacturing cost as well.